In the paradigm of stochastic computation, digital logic may be used to perform computation on random bit streams, where numbers are represented by the probability of observing a one. A benefit of such a stochastic representation may be that complex operations can be performed with very simple logic. For instance, multiplication may be performed with a single AND gate and scaled addition can be performed with a single multiplexer unit. One drawback may be that the computation has very high latency, due to the length of the bit streams. Another drawback may be that the computation suffers from errors due to random fluctuations and correlations between the streams. These effects may worsen as the circuit depth and the number of inputs increase.
A certain degree of accuracy may be maintained by re-randomizing bit streams, but this is an additional expense. While the logic to perform the computation is simple, generating random or pseudorandom bit streams is costly. The random or pseudorandom sources required to generate the representation are costly, consuming a majority of the circuit area (and diminishing the overall gains in area). For example, pseudorandom constructs such as linear feedback shift registers (LFSRs) may account for as much as ninety percent of the area of stochastic circuit designs. This design may significantly diminish the area benefits.